1. Field of the Invention
The present invention relates to a BiMIS circuit which may include a BiCMOS circuit.
2. Description of the Prior Art
LSI BiCMOS circuits (hereinafter referred to as "BiMIS circuits" in a broader sense) of silicon semiconductors which are most widely used at present are attracting much attention because they are characterized by both the high-speed operation of bipolar transistors (BJTs) and the high degree of integration and low power requirements of CMOS circuits (complementary MIS circuits) composed of MOSFETs (hereinafter referred to as "MISFETs").
FIG. 1 of the accompanying drawings shows a basic arrangement of a conventional BiMIS circuit. FIG. 2 of the accompanying drawings illustrates a conventional BiCMOS circuit. FIG. 3 of the accompanying drawings shows a conventional BiNMOS circuit. The BiCMOS circuit shown in FIG. 2 and the BiNMOS circuit shown in FIG. 3 are collectively called BiMIS circuits.
Basic operation of the BiMIS circuit shown in FIG. 1 will be described below.
In the BiMIS circuit, the base node of a BJT 15 is charged by a drain current Id of a PMOSFET 16 so that the potential at the base node becomes a turn-on voltage V.sub.F or higher, thus turning on (rendering conductive) the BJT 15, and the base node of the BJT 15 is discharged by a drain current Id of an NMOSFET 17 so that the potential at the base node becomes the turn-on voltage V.sub.F or lower, thus turning off (rendering nonconductive) the BJT 15. The BiMIS circuit quickly charges and discharges an external load capacitance CL based on the large load drive capability of the BJT 15.
A delay time .tau.pd of the BiMIS circuit at the time the external load capacitance CL is charged and discharged is given by: EQU .tau.pd=(CEBV.sub.F)/Id+(1/2)(CLVCC)/Ic (1)
where CEB is the emitter-to-base capacitance of the BJT 15, V.sub.F the turn-on voltage of the BJT 15, Id the drain current of the MOSFETs 16, 17, CL the external load capacitance, VCC a high-potential power supply voltage, and Ic the collector current of the BJT 15.
The first term of the equation (1) represents the self delay time of the BiMIS circuit in which the MOSFETs 16, 17 turn on and off the BJT 15. The second term of the equation (1) represents the time in which the BJT 15 charges and discharges the external load capacitance. Since the turn-on voltage V.sub.F of the BJT 15 is determined substantially by the band gap of a semiconductor which constitutes the base of the BJT 15, turn-on voltage V.sub.F of the BJT 15 is about 0.8 V if the BJT 15 comprises a bipolar transistor of silicon. The emitter-to-base capacitance CEB is determined by the area of the emitter of the BJT 15.
Logic levels and an output logic amplitude of the BiMIS circuit will be described below with reference to FIGS. 2 and 3 of the accompanying drawings.
When a signal of low level is applied to an input terminal 11 of the BiCMOS circuit shown in FIG. 2, a PMOSFET 26 is turned on, an NMOSFET 27 is turned off, an NMOSFET 29 is turned off, and an NMOSFET 30 is turned on. Therefore, a BJT 25 is turned on and a BJT 28 is turned off. Since the PMOSFET 26 is turned on, the potential at the base of the BJT 25, which serves as a load pull-up transistor, is held at a high potential VCC of a high-potential power supply terminal 13. The potential at the collector of the BJT 25 is also kept at the high potential VCC as the collector is connected to the high-potential power supply terminal 13. Therefore, the potential at the emitter of the BJT 25 which is connected to an output terminal 12 is equal to the difference between the potential at the base of the BJT 25 and a turn-off voltage V.sub.F of the BJT 25. The BiCMOS circuit shown in FIG. 2 thus outputs a high-level output voltage VOH (VCC-V.sub.F) from the output terminal 12.
When a signal of high level is applied to the input terminal 11, the PMOSFET 26 is turned off, the NMOSFET 27 is turned on, the NMOSFET 29 is turned on, and the NMOSFET 30 is turned off. Therefore, the BJT 25 is turned off and the BJT 28 is turned on, applying a low-level signal to the output terminal 12. The potential at the emitter of the BJT 28, which serves as a load pull-down transistor, is held at a low potential GND of a low-potential power supply terminal 14. Since the NMOSFET 29 is turned on, the potential at the base of the BJT 28 rises higher than the potential (GND+V.sub.F) which is a turn-on voltage of the BJT 28 higher than the emitter potential by V.sub.F. The BiMIS circuit outputs the potential (GND+V.sub.F) at the base of the BJT 28 as a low-level output voltage VOL from the output terminal 12. Consequently, the BiCMOS circuit shown in FIG. 2 has an output logic amplitude VL (VCC-2 V.sub.F).
When a signal of low level is applied to an input terminal 11 of the BiNMOS circuit shown in FIG. 3, a PMOSFET 46 is turned on, an NMOSFET 47 is turned off, and an NMOSFET 48 is turned off. Therefore, a high-level output voltage VOH of the BiNMIS circuit shown in FIG. 3 is of the same value (VCC-V.sub.F) as the high-level output voltage of the BiCMOS circuit shown in FIG. 2.
When a signal of high level is applied to the input terminal 11, the PMOSFET 46 is turned off, the NMOSFET 47 is turned on, and the NMOSFET 48 is turned on. Therefore, the BJT 45 is turned off, applying a low-level output voltage to the output terminal 12. Since the NMOSFET 48 is turned on, the low-level output voltage is of a low potential GND. Therefore, the BiNMOS circuit shown in FIG. 3 has an output logic amplitude VL (VCC-V.sub.F).
As disclosed in "BiCMOS Technology" (Kubo, et al., Electronic Information Communication Society, page 49) the conventional BiMIS circuit has a problem in that at low voltages of 3.3 V or less, it has an increased delay time and cannot maintain its speed advantage over the CMOS circuits. More specifically, as the power supply voltage of the conventional BiMIS circuit drops, the output logic amplitude of the conventional BiMIS circuit is lowered, thus causing the source-to-gate voltage VSG of a MOSFET in the input stage of the BiMIS circuit to drop, with a resulting reduction in the drain current Id of the MOSFET. Specifically, when the power supply voltage is reduced, the first term of the equation (1) abruptly increases, bringing about an increase in the delay time .tau.pd of the BiMIS circuit. The second term of the equation (2) is dependent on the characteristics of the BJT and the external load, and less dependent on the power supply voltage. As a consequence, when the power supply voltage is lowered, the delay time of the BiMIS circuit is increased.
If the high-potential power supply voltage is indicated by VCC and the low-potential voltage by GND, then the BJT 25 (see FIG. 2) has a base potential of up to VCC and a collector potential of VCC, with the result that the potential at its emitter as the output node does not exceed (VCC-V.sub.F). Furthermore, since the BiCMOS circuit shown in FIG. 2 employs the BJTs 25, 28 which serve as load pull-up and pull-down transistors, respectively, for the output terminal 12 and which have a high load driving capability, the BiCMOS circuit can rapidly charge and discharge the load connected to the output terminal 12. However, inasmuch as the base and collector of the BJT 28 are short-circuited to discharge the load capacitance for reducing the load voltage, the load voltage cannot be made lower than the voltage V.sub.F. The output logic amplitude of the BiCMOS circuit shown in FIG. 2 is thus equal to the power supply potential (VCC-2 V.sub.F). If the BiCMOS circuit drives a MISFET in a next stage, then the source-to-gate voltage VSG of the MOSFET in the next stage drops, preventing it from operating at high speed.
The BiNMOS circuit shown in FIG. 3 has the NMOSFET 48 as a load pull-down transistor for lowering the voltage of the load to the GND level. The BiNMOS circuit has an output logic amplitude (VCC-V.sub.F) which is higher than the logic amplitude of the BiCMOS circuit shown in FIG. 2 by the voltage VF. However, the MOSFET 48 does not have as large a driving capability as the BJT. If the MOSFET 48 is to be given as large a driving capability as the BJT, then the size and hence the input capacity of the MOSFET 48 will be increased, resulting in an increase in the time required to lower the output voltage.